In electronic systems, timing signals can be very important to the overall performance of the system. One widely used way to synchronize operations of a system (e.g., integrated circuit) with an externally received clock can be with a phase locked loop (PLL). PLLs can address many common timing problems associated with generating a clock signal, including but not limited to, unwanted clock skew and jitter. Of course, PLLs are widely in used in applications other than frequency synchronization, including but not limited to frequency synthesis, frequency translation, frequency detection, and frequency modulation.
To better understand various features of the disclosed embodiments, a conventional PLL arrangement will now be described with reference to FIG. 9.
FIG. 9 shows a block schematic diagram of a conventional third order PLL designated by the general reference character 900. FIG. 9 shows a basic “charge pump” style PLL, in which a charge pump generates a control (or error) voltage on a capacitance by “pumping” the potential up or down. Such a basic charge pump style PLL is commonly used for frequency synthesis applications.
A PLL 900 can include a phase frequency detector 902, charge pump 904, a loop filter (with passive components resistor RL, capacitor CL, and capacitor CS) 906, a voltage controlled oscillator (VCO) 908, and a feedback divider 910. These blocks of a PLL 900 can form a negative feedback loop that operates to match the phases and frequencies of the two PFD input signals, φIN and φFBK. A feedback divider 910 can allow the synthesized output signal to operate at “P” times the input frequency, thus enabling the PLL to generate an output signal φOUT in phase but greater in frequency than the reference input signal φIN.
Because a PLL is a feedback loop, a loop frequency response can be important for determining the stability of the overall circuit. In order for a loop to be stable, the total loop phase shift must typically be less than 180 degrees when the open loop gain falls below 0 dB (at the open loop bandwidth).
In a basic charge pump PLL, the stable loop frequency range in the PLL can be far less variable over process and environmental conditions (due mostly to RC component variations of the loop filter) than the open loop bandwidth. Therefore, knowledge of the open loop bandwidth within the less variable stable loop frequency range can show the relative stability of the PLL. For example, if the open loop bandwidth is beyond the stable loop frequency range window, one can reasonably infer either instability or well under-damped stability.
Utilizing the transfer functions shown in FIG. 9, the PLL open loop bandwidth can be found as shown in Eq. 2.1.
                              OLG          ⁡                      (            s            )                          =                ⁢                              I            CP                    ×                                                    s                ⁢                                                                  ⁢                                  τ                  L                                            +              1                                                      s                ⁡                                  (                                                            C                      L                                        +                                          C                      S                                                        )                                            ⁢                              (                                                      s                    ⁢                                                                                  ⁢                                          τ                      S                                                        +                  1                                )                                              ×                                    K              VCO                        s                    ×                      1            P                                              Eq        .                                  ⁢        2.1                        where                                                                            τ            L                    =                    ⁢                                    R              L                        ⁢                          C              L                                      ,                              τ            S                    =                                                                      C                  L                                ⁢                                  C                  S                                                                              C                  L                                +                                  C                  S                                                      ⁢                          R              L                                      ,                                                    at                                                                            OLG            ⁢                          (              s              )                                ≈                    ⁢                      0            ⁢                                                  ⁢            dB                          ,                                                                      OLG          ⁡                      (            s            )                          =                                                                              K                  VCO                                ⁢                                  I                  CP                                                            P                ⁡                                  (                                                            C                      L                                        +                                          C                      S                                                        )                                                      ×                                          s                ⁢                                                                  ⁢                                  τ                  L                                                            s                2                                              =                                                    K                VCO                            ⁢                              I                CP                            ⁢                              R                L                            ⁢                              C                L                                                    P              ⁡                              (                                                      C                    L                                    +                                      C                    S                                                  )                                                                                                        OLBW        =                ⁢                              K            VCO                    ⁢                      I            CP                    ⁢                      R            L                    ×                                    C              L                                      P              ⁡                              (                                                      C                    L                                    +                                      C                    S                                                  )                                                                                    
While measurement of PLL loop dynamics, including the open loop bandwidth, can provide insight into loop stability, such measurements are conventionally taken by bench and pico-probe testing whereby individual PLL component measurements are taken by an individual. Such methods present a more complex or invasive method than could be achieved through automated chip/part testing. As result, such approaches can be slow, inefficient, and expensive. Therefore, full PLL testing, which includes the open loop bandwidth measurement, is typically only completed on a small sample set of any particular PLL chip/part taken from a much larger manufacturing lot or group of devices.
Conventional PLL test measurements taken during production typically include only a “lock” test, which can reveal PLL stability in a binary sense (true/false), but reveals no other information about the PLL loop dynamics.
In light of the above, it would be desirable to have a test mechanism for testing PLL loop dynamics that can be more easily and inexpensively implemented than conventional approaches, such as bench testing.